Kafil M. Razeeb, Eric Dalton, Graham Lawerence William Cross, Anthony James Robinson


Packaging electronic devices is a growing challenge as device performance and power levels escalate. As device feature sizes decrease, ensuring reliable operation becomes a challenge. Ensuring effective heat transfer from an integrated circuit and its heat spreader to a heat sink is a vital step in meeting this challenge.

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The projected power density and junction-to-ambient thermal resistance for high-performance chips at the 14 nm generation are >100 Wcm−2 and <0.2 °CW−1, respectively. The main bottleneck in reducing the net thermal resistance are the thermal resistances of the thermal interface material (TIM). This review evaluates the current state of the art of TIMs. Here, the theory of thermal surface interaction will be addressed and the practicalities of the measurement techniques and the reliability of TIMs will be discussed. Furthermore, the next generation of TIMs will be discussed in terms of potential thermal solutions in the realisation of Internet of Things.


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a Tyndall National Institute, University College Cork, Cork, Ireland

b Stokes Laboratories, University of Limerick, Limerick, Ireland

c School of Physics, CRANN Nanotechnology Institute, Trinity College Dublin, Dublin 2, Ireland

d Department of Mechanical & Manufacturing Engineering, Trinity College Dublin, Dublin 2, Ireland

e CONNECT, Dunlop Oriel House, Trinity College, Dublin, Ireland